This invention relates generally to logic circuits and more particularly to logic circuits adapted for very large scale integrated (VLSI) circuit layouts.
As is known in the art, CMOS (complementary metal oxide semiconductor) transmission-gate based logic circuits have been used as efficient solutions for generating specific logic functions. Such CMOS transmission-gate circuits typically includes a P-channel and an N-channel MOS transistor having gates fed by a complementary logic signal. The source electrodes are connected together to form a common input fed by a second logic signal and the drains are connected together to form a common output. Thus, when the first logic signal is at a first logic state, the second logic signal is coupled through the gate and appears at the output, and conversely, when the first logic signal is at a second, complementary logic state, the second logic signal is inhibited (i.e. decoupled) from passing to the output. One logic function implemented with such CMOS transmission-gates is an Exclusive-OR gate such as is shown in the High-Speed CMOS Logic Data Book published by Texas Instruments, 1984 on page 7-4. Here, a pair of CMOS transmission-gates are provided with the outputs thereof connected in common to provide the output for the Exclusive-OR gate. The true and complement of the second logic signal are fed to the input of a corresponding one of the transmission-gates. The true and complement of the first logic signal are fed to the transmission-gates such that when the first logic signal is in a first logic state (say true), the complement of the second logic signal passes through one of the transmission-gates to the output of the Exclusive-OR gate and conversely, when the first logic signal is in the second state (i.e. complement), the true of the second logic signal passes the other one of the transmission-gates to the output of the Exclusive-OR qate. A further "ad hoc" simplification of a CMOS Exclusive-OR gate is shown and described in U.S. Pat. No. 4,417,161 to Masaru Uya and assigned to Matsushita Electric Industrial Co., Ltd. Thus, CMOS transmission-gates have been shown to minimize area and delay when implemented on a CMOS based VLSI chip. However, there does not appear to be a uniform approach to the creation of these special circuit solutions. For example, Boolean functions (i.e. OR, AND, NOR and NAND) are typically realized using conventional state CMOS logic technology by combining ordered arrangements of NAND and NOR gates.
A conventional CMOS NOR gate typically includes a plurality of N-channel MOS transistors, one for each input to the gate and a like plurality of P-channel MOS transistors. The sources-drains of the N-channel transistors are coupled in shunt between ground and the output; each gate is fed by a corresponding logic signal. The sources-drains of the P-channel transistors are serially connected between +V.sub.DD and the output; each gate also being fed by a corresponding one of the logic signals. Hence, if any one of the logic signals is "high", the N-channel transistor fed by such signal conducts bringing the output towards ground. However, if all logic signals are "low", the N-channel devices are non-conducting and the P-channel devices turn on pulling the output up to +V.sub.DD. Thus, the series connection of the P-transistors result in a long delay time when responding to all "high" input signals unless their W/L ratios are increased in proportion to the number of serial transistors. In fact, when the serial chain exceeds five, distribution effects are similar to an R-C delay line.
For the NAND gate, a similar, yet complementary, effect exists. In this case, the N-channel transistors are serially coupled between the output and ground; each one having its gate coupled to a corresponding one of the input signals. The P-channel transistors are coupled in parallel between +V.sub.DD and the output; each one having its gate coupled to a corresponding one of the inputs. Thus, if any one of the inputs is "low", the P-channel transistors fed by it conducts and the output is at +V.sub.DD ; however, when all of the inputs go "high", all of the N-channel transistors go towards conduction driving the output towards ground. Thus, in this case, the W/L ratios of the N-channel transistors must be increased in proportion to the number of those in series. Further, with the NOR gate, since the carrier (hole) mobility of the P-channel transistors is lower than that of the carrier (electron) mobility of the N-channel transistor, the W/L ratio of the P-channel transistor must be typically larger than that of the N-channel transistor in order to obtain balanced dynamic performance. This, however, results in a very large area consumption for multi-input NOR gates in order to preserve logic "1" output speed. In order to overcome these problems, a number of other circuit forms have been developed. Among these are pre-charge logic, programmable logic arrays, domino-logic, etc. These are typically "dynamic" in form and impose additional constraints on system timing (as well as logic structuring).